module cfg_UART_tb();

wire [23:0] cfg_datao;
wire frm_rdy;
wire [15:0] resp;

reg [23:0] cmd_data;
reg clk, rst_n, snd_frm, clr_frm_rdy, snd_rsp;
reg [15:0] rsp_data;
wire rsp_rdy;

wire tx_rx, rx_tx;

cfg_mstr DUT1(cmd_data, snd_frm, resp, rx_tx, tx_rx, clk, rst_n, rsp_rdy);
cfg_UART DUT3(tx_rx, rx_tx, clk, rst_n, rsp_data, clr_frm_rdy, snd_rsp, frmrdy, cfg_datao);

initial begin
	clk = 1'b0;
	rst_n = 1'b0;
	cmd_data = 24'hFFF;
	snd_frm = 1'b0;
	clr_frm_rdy = 1'b0;
	snd_rsp = 1'b0;
	rsp_data = 16'hFF;
end

always
	#1 clk = !clk;

initial begin
	$monitor("snd_frm: %b, data In: %h, frmrdy: %h, data Out: %h,  T: %t", 
		snd_frm, cmd_data, frmrdy, cfg_datao, $time);
	rst_n = 1'b0;
	#5 rst_n = 1'b1;
	cmd_data = 24'h696;
	snd_frm = 1;
	@(posedge clk)
	@(posedge clk)
	snd_frm = 0;
	@(posedge frmrdy)
	#500000 $monitor("snd_rsp %b, rsp_data %h, rsp_rdy %b, resp %h", snd_rsp, rsp_data, rsp_rdy, resp);
	rsp_data = 16'h4562;
	snd_rsp = 1;
	@(posedge clk)
	@(posedge clk)
	snd_rsp = 0;
	@(posedge rsp_rdy)
	#23	$finish;
end
endmodule
